DIVST=OUTPUT_HIGH, DBGMD=HALT, OVFIEN=DISABLED
Module Control
| OVFIEN | PCA Counter Overflow/Limit Interrupt Enable. 0 (DISABLED): Disable the PCA counter overflow/limit event interrupt. 1 (ENABLED): Enable the PCA counter overflow/limit event interrupt. |
| DBGMD | PCA Debug Mode. 0 (HALT): A debug breakpoint will cause the PCA to halt. 1 (RUN): The PCA will continue to operate while the core is halted in debug mode. |
| DIVST | Clock Divider Output State. 0 (OUTPUT_HIGH): The clock divider is currently in the first half-cycle. 1 (OUTPUT_LOW): The clock divider is currently in the second half-cycle. |
| DIV | Current Clock Divider Count. |